1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular, to the structure and pattern layout of a logic circuit which is preferably applied to a decoder circuit of semiconductor memory devices or the like.
2. Description of the Related Art
Conventional decode circuits in semiconductor memory devices have the function of selecting a specific address in a memory cell, and the decoder circuits generally employ, for example, a two-input NAND circuit explained below. FIG. 12 is a circuit diagram showing an example of such a NAND circuit.
The shown NAND circuit 100 consists of a logic section 101 using CMOS transistors, and an output section 102 using bipolar and MOS transistors.
The logic section 101 includes a parallel-connected circuit employing two pMOS (i.e., p-channel MOS) transistors M51, and M52, and a serially connected circuit employing two nMOS (i.e., n-channel MOS) transistors M53 and M54. The parallel-connected circuit and the serially-connected circuit are further serially connected in this order between a high-potential power supply line 103 (i.e., voltage=Vcc) and an earth (or grounding) line 104.
Among two input signals A and B to be logically operated, signal A is input into the gate electrodes of pMOS transistor M51 and NMOS transistor M53, while signal B is input into the gate electrodes of pMOS transistor M52 and NMOS transistor M54. A signal resulting from this operation is output from a common drain electrode of pMOS transistors M51 and M52, and nMOS transistors M53 and M54 to output section 102.
In the output section 102, bipolar transistor (abbreviated to xe2x80x9cBiP-Trxe2x80x9d, hereinafter) Q1 whose collector electrode is connected to the power supply line 105, and two nMOS transistors M55 and M56 are serially connected in this order between the power supply line 105 and earth line 106, as shown in FIG. 12. A logic signal from logic section 101 is input into the base electrode of BiP-Tr Q1, and input signals A and B are respectively input into the gate electrodes of the NMOS transistors M55 and M56. This two-input Bi-CMOS NAND circuit uses the contact of the drain electrode of the nMOS transistor M55 and the emitter electrode of the BiP-Tr Q1 in the output section as an output terminal from which output signal X0 is output.
In the NAND circuit 100 as shown in FIG. 12, when both signals A and B are high, the serially connected nMOS transistors M53 and M54 are on (i.e., in the ON states), while the parallel-connected pMOS transistors M51 and M52 are off (i.e., in the OFF states). As a result, the electric potential of the base electrode of the BiP-Tr Q1 becomes ground level, so that the transistor is set to the OFF state. In addition, the serially connected nMOS transistors M55 and M56 are switched on, so that the electric charges of a load (not shown) are discharged via these transistors M55 and M56, and the level of the output signal X0 becomes low.
In contrast, when signal A or B is low, one of the NMOS transistors M53 and M54 is off; thus, these nMOS transistors M53 and M54 have no effect on the decrease of the base potential of the BiP-Tr Q1. Here, one of the pMOS transistors M51 and M52 is on; therefore, the above pMOS transistors M51 and M52 increase the electric potential of the base of the BiP-Tr Q1. As a result, the voltage at the base of the BiP-Tr Q1 is increased to Vcc, and the transistor is switched on. On the other hand, one of the serially connected nMOS transistors M55 and M56 is switched off, so that these transistors have no effect on the discharge from the output terminal. As a result, according to the charging operation using the BiP-Tr Q1, the level of the output signal X0 becomes high.
That is, the output from circuit 100 as shown in FIG. 12 is low only when both of the two inputs are high, and in other cases, the output is high based on the NAND logic. Decoder circuits provided in semiconductor storage devices or the like often employ logic circuits as explained above. Here, a feature of the circuit operation is that only one of arrayed NAND gates outputs a low level signal (i.e., LOW signal) as a selected output, and the others output high level signals (i.e., HIGH signals) as non-selected outputs. In the decoder circuit, a plurality of such gate structures are connected, and the memory cell designated by an input address can be selected.
In the above conventional NAND circuit, the level of the output signal can be made high by using the BiP-Tr Q1 to which the base current is supplied using the pMOS transistors M51 and M52. Therefore, sufficient current can be supplied, and the operation speed can be high. However, the level of the output signal can be made low by (i) decreasing the potential of the base of the BiP-Tr Q1 by using the serially connected nMOS transistors M53 and M54, and (ii) drawing electric charges (i.e., current) from an output load by using the serially connected nMOS transistors M55 and M56. This means that in the nMOS transistor, the equivalent gate length is double while the current supplying ability is half, compared with the other cases.
In order to compensate for the reduction (by half) of the current supplying ability, generally, the gate width of the nMOS transistor is designed to be wider so as to improve the current supplying ability and to prevent a delay in the speed of the drop in potential. However, the increase of the gate width causes an increase of the input capacitance observed from the input signal side; thus, the operation speed of the logic circuit as the former stage is decreased. That is, in order to improve the operation speed of a circuit having a plurality of logic gates, it is necessary to improve the fan-out characteristics (i.e., the relationship between the ratio of the capacitance of the output (load) to the capacitance of the input, and the delay time). However, the degradation of the current supplying ability of the serially connected nMOS transistors is an obstacle which must be overcome to improve the fan-out characteristics. In addition, the increase of the gate width obviously causes an increase of the area of the logic circuit.
As for the decoder circuit, the speed of the selecting operation, which is a characteristic operation of this circuit, depends on the delay time of the output selected signal. Here, the selecting operation is performed by decreasing the output level by using serially connected nMOS transistors (or by increasing the output level by using serially connected pMOS transistors in case of a NOR circuit). Therefore, the decrease of the current supplying ability with respect to the serially connected MOS transistors has a considerable effect on the operation speed.
In order to solve the operational delay, increase of the occupied area, and the like in such logic circuits, the inventors of the present invention proposed the logic circuit, having a structure as shown in FIGS. 13 and 14, which is disclosed in Japanese Unexamined Patent Application, First Publication, No. Hei 9-200036.
In the conventional circuit shown in FIG. 12, each of the current path for decreasing the potential of the base of the BiP-Tr Q1 and the current path for drawing electric charges from an output load is formed using two serially connected nMOS transistors. In contrast, the circuit 200 in FIG. 13, each path (here, the BiP-Tr Q2 is used) is formed using a single nMOS transistor M63 or M64. Among two input signals A and B, ∇B (here, ∇ represents an upper bar indicating inversion, hereinafter), the inverted signal of input signal B, is input into the source electrodes of the nMOS transistors M63 and M64. The same logic as that realized in the circuit shown in FIG. 12 can also be realized in the circuit 200. In the structure of circuit 200, the input capacitance is half as much as that of the conventional gate-input capacitance, and the fan-out characteristics can be improved. Additionally, the nMOS transistor M64 functions as a transfer gate; thus, current drawing from the output terminal is started before the ON operation by the gate input. Therefore, the operation speed of the whole circuit (also including the logic circuit) can be very high. However, in this structure, the load capacitance at the output terminal is discharged via a wiring line of ∇B, an input signal. Therefore, in order to perform a high speed operation, it is necessary to satisfy a condition that the load capacitance of inverted signal ∇B is larger than the load capacitance of the output terminal. In comparison with the conventional circuit using 7 transistors, only 5 transistors are used in the whole circuit in the present example, thereby reducing the occupied area of the logic circuit.
The circuit 300 as shown in FIG. 14 has the same structure of the NAND logic circuit as that of the NAND circuit using a bipolar CMOS structure as shown in FIG. 13, but has the difference that a CMOS inverter is added to the output point of the NAND circuit so as to form an AND logic circuit. The load driving ability of CMOS circuits is generally lower than that of bipolar CMOS circuits. Therefore, in order to drive a large load, an inverter for driving the same is connected to the logic circuit. In the decoder circuit using the present structure, most of the decoder outputs are not selected, and only at the selected output, the output load of the NAND logic can be active via the source electrode of the NMOS transistor. In this case, the load capacitance of the relevant NAND output only corresponds to the input capacitance of the CMOS inverter for the driving operation; therefore, almost all of the load capacitance of the decoder outputs corresponds to the sum of the input and wiring capacitance of the non-selected channels. Therefore, the above conditions for improving the operation speed can be easily satisfied, and the high-speed operation can be efficiently performed. Also in this circuit, the number of necessary transistors can be decreased from 7 (in the conventional case) to 5, thereby reducing the occupied area of the logic circuit.
As explained above, the circuits as shown in FIGS. 13 and 14 are effective for improving the operation speed, but still insufficient for reducing the occupied area. In semiconductor storage. devices, the memory cell area having regularly arrayed elements has been reduced because the size of each cell has been reduced; however, in the peripheral circuit area including the decoder circuit, area reduction remains difficult because the relevant elements are not regularly arranged. The demand for reduction of chip size has increased, and reduction of the occupied area of peripheral circuits such as the decoder circuit has received much attention.
In consideration of the above circumstances, an objective of the present invention is to provide a semiconductor integrated circuit in which the area of the logic circuit is reduced so that the area of the peripheral circuits such as the decoder circuit can be reduced, thereby reducing the chip size.
Therefore, the present invention provides a semiconductor integrated circuit having a logic circuit which comprises:
one or more first transistors for supplying electric charges to an external load via an output terminal; and
one or more second transistors for drawing electric charges from the load via the output terminal; and wherein:
in the logical operation of the logic circuit, the above supply and drawing of electric charges are executed according to combination of the states of a plurality of binary logic signals input from an external device; and
among all the transistors in the logic circuit, each transistor other than the first transistors for supplying electric charges has a threshold voltage value lower than that of each first transistor.
The inventors of the present invention worked to reduce the occupied area of a conventional AND logic circuit (as shown in FIG. 14), and found that the size of each MOS FET as a constituent of the logic circuit can be reduced by reducing the threshold voltage value (called Vth, hereinbelow) of the FET, and accordingly, the size of the whole circuit can be reduced. That is, to reduce Vth of the MOS FET causes an increase of current flowing when a predetennined voltage is applied to the gate electrode, so that the ability to drive a transistor is improved and a smaller gate width is sufficient for providing a specific current. Therefore, according to the reduction of the threshold voltage value Vth of the MOS FETs in the logic circuit, the size of each transistor can be reduced and the occupied area of the whole logic circuit can be reduced.
According to the above, it is most preferable that Vth of all of the MOS FETs in the logic circuit be reduced. However, this cannot be realized in some kinds of logic circuits. This is due to a strong demand of reduction of power consumption as well as the reduction of the chip size in the current development of semiconductor integrated circuits.
For example, when the circuit shown in FIG. 14 is used as a decoder circuit, the output terminal is connected to a word line, and when the output to the word line is low (i.e., the signal level is low), the operation is in a standby mode. Under this condition, the nMOS transistor for drawing electric charges from the word line is on while the pMOS transistor for supplying electric charges to the word line is off. If it is assumed that the threshold voltage value Vth of the pMOS transistor for supplying electric charges be reduced (according to the above-considered reduction of all the MOS FETs), then the leakage current of the relevant pMOS transistor in the OFF state is considerably increased because a high voltage Vcc is directly applied to the source electrode of the pMOS transistor. This increase of the leakage current causes an increase of the standby current, thereby increasing the power consumption. Accordingly, Vth of the transistor for supplying electric charges, which is in the OFF state in the standby mode of the circuit operation and which is connected to high voltage Vcc, cannot be reduced.
Generally, such a logic circuit is formed using transistors having a specific Vth. However, in the present invention, low and high threshold voltage values Vth (the high value corresponds to the above specific Vth which is generally used) are used in a single circuit, that is, a xe2x80x9cmulti-Vthxe2x80x9d method is applied to such a logic circuit. Accordingly, the gate width of each transistor having a low Vth can be reduced in comparison with the conventional case, thereby reducing the occupied area of the whole circuit.
The present invention also provides a more specific semiconductor integrated circuit having an AND logic circuit which comprises:
a NAND circuit which includes:
parallel-connected first and second p-channel MOS FETs, where first and second input signals are respectively input into the gate electrodes of the FETs; and
a first n-channel MOS FET, where the first input signal is input into the gate electrode and an inverted signal of the second input signal is input into the source electrode, and
wherein the common drain electrode of the first and second p-channel MOS FETs and the drain electrode of the first n-channel MOS FET are connected; and
an inverter circuit having a complementary MOS transistor structure for receiving an output signal from the NAND circuit and outputting an inverted signal of the received signal from an output terminal, where the complementary MOS transistor structure comprises a third p-channel MOS FET and a second n-channel MOS FET, and
wherein among all the MOS FETs in the AND logic circuit, each FET other than the third p-channel MOS FET has a threshold voltage value lower than the threshold voltage value of the third p-channel MOS FET.
This structure is obtained by applying the concept of the present invention to the AND logic circuit as shown in FIG. 14 (which is a previous invention of the inventors). Among the five transistors (three pMOS FETs and two nMOS FETs), the threshold voltage value Vth of each of the four transistors other than the third pMOS FET can be reduced, thereby sufficiently reducing the occupied area of the whole logic circuit.
The present invention also provides another specific semiconductor integrated circuit having an AND logic circuit which comprises:
a NAND circuit which includes:
a first pMOS FET, where a fixed electric potential is applied to the gate electrode so as to keep the first MOS FET on; and
a first n-channel MOS FET, where a first input signal is input into the gate electrode and a second inverted input signal is input into the source electrode, and
wherein the drain electrode of the first p-channel MOS FET and the drain electrode of the first n-channel MOS FET are connected; and
an inverter circuit having a complementary MOS transistor structure for receiving an output signal from the NAND circuit and outputting an inverted signal of the received signal from an output terminal, where the complementary MOS transistor structure comprises a second p-channel MOS FET and a second n-channel MOS FET, and
wherein among all the MOS FETs in the AND logic circuit, each FET other than the second p-channel MOS FET has a threshold voltage value lower than the threshold voltage value of the second p-channel MOS FET.
In this structure, only two input signals, the first input signal and the second inverted input signal are necessary, and the number of necessary transistors can be reduced by one in comparison with the previous structure. Accordingly, the occupied area of the logic circuit can be further reduced also by reducing the threshold voltage value Vth.
The present invention also provides a semiconductor integrated circuit having a NOR logic circuit which comprises:
a first pMOS FET, where a first input signal is input into the gate electrode and an inverted signal of a second input signal is input into the source electrode; and
parallel-connected first and second nMOS FETs, where the first and second input signals are respectively input into the gate electrodes of the FETs, and wherein:
the drain electrode of first pMOS FET and the common drain electrode of the first and second NMOS FETs are connected; and
the threshold voltage value of each of the MOS FETs in the NOR logic circuit may be decreased.
The NOR logic circuit having the above structure has a relatively high ability to drive a load; thus, no inverter circuit for driving a load is necessary. In addition, this logic circuit includes no transistor (for supplying electric charges) which is off in the operation-standby mode and which is connected to a high voltage Vcc. Therefore, all of the transistors can have low threshold voltage value Vth, and have an effect on the reduction of the occupied area of the logic circuit.
The logic circuits as explained above may be applied to a decoder circuit.
The present invention also provides a semiconductor integrated circuit comprising:
a decoder area, positioned between adjacent memory cell areas, having one or more p-channel MOS FETs and one or more n-channel MOS FETs, wherein:
each of the p-channel MOS FETs and n-channel MOS FETs is arranged in a manner such that the direction of the gate width is perpendicular to the direction along which word lines extend in the memory cell areas.
As explained above, in the logic circuits according to the present invention which include transistors having low threshold voltage values Vth, the gate width of each relevant transistor can be reduced. Therefore, even if each transistor is arranged in a decoder area in a manner such that the direction of the gate width is perpendicular to the direction along which the word lines extend (that is, arranged in the longitudinal direction), all the transistors can be arranged within the longitudinal range of a predetermined number of memory cells, so that the occupied area of the whole decoder area can be reduced.
In the above structure, the p-channel MOS FETs and the n-channel MOS FETs may be aligned in a direction perpendicular to the direction along which word lines extend in the memory cell areas, in a manner such that the p-channel MOS FETs and the n-channel MOS FETs face each other.
In the general conventional arrangement of the decoder area, the p-channel MOS FETs and the n-channel MOS FETs are aligned in the transverse direction, that is, in a direction parallel to the direction along which word lines extend in the memory cell areas. In contrast, in the decoder area of the semiconductor integrated circuit according to the present invention, the conventional arrangement can be rotated by 90 degrees, so that the width (in the direction along which the word lines extend) of the decoder area between the memory cell areas can be reduced.
In the general decoder area, a main power supply line for supplying electric power is provided in and along each boundary between the decoder area and each of the memory cell areas. However, if the the p-channel MOS FETs and the n-channel MOS FETs are aligned in a direction parallel to the direction along which the word lines extend, then power supply lines can extend from each main power supply line towards the area where the p-channel MOS FETs are formed, but cannot pass through the area where the n-channel MOS FETs are formed. Therefore, the main power supply lines which face each other via the decoder area cannot be connected.
In contrast, in the present invention, the p-channel MOS FETs and the n-channel MOS FETs are aligned in a direction perpendicular to the direction along which word lines extend in the memory cell areas, in a manner such that the p-channel MOS FETs and the n-channel MOS FETs face each other. In this case, power supply lines (first sub power supply lines) which cross the decoder area and extend parallel to the direction along which the word lines extend can be provided in the area where the p-channel MOS FETs are formed, so as to connect the main power supply lines using the first sub power supply lines. As a result, the voltage drop in the power supply lines can be reduced, and the resistance of the power supply lines can be reduced, thereby providing improved power supply lines. In addition, the width of each power supply line can be reduced.
In addition, the main power supply lines at both sides of a memory cell area may be connected via second sub power supply lines which cross the memory cell area. Accordingly, over the whole chip area of the semiconductor integrated circuit, power supply lines are arranged and electrically connected, thereby forming a wiring network. Therefore, the power supply lines can be much more efficiently arranged, and the above-explained effects can be much more easily obtained.
The above-explained wiring structure can also be applied to earth lines.
That is, when a main earth line for grounding is provided in and along each boundary between the decoder area and each of the memory cell areas, the main earth lines in the boundaries can be connected via first sub earth lines which cross the decoder area and extend parallel to the direction along which the word lines extend.
In addition, the main earth lines at both sides of a memory cell area can be connected via second sub earth lines which cross the memory cell area, and the main earth lines, and the first and second sub earth lines may form a wiring network for grounding over the whole chip area of the semiconductor integrated circuit.
In the above-explained distinctive pattern layout of the decoder area, the p-channel MOS PETs and the n-channel MOS FETs may form a NAND circuit, an AND logic circuit comprising a NAND circuit and an inverter circuit, NOR circuit, or the like.
As explained above, according to the present invention, the area of the logic circuit can be reduced, thereby reducing the area of the decoder circuit, peripheral circuit, or the like. Therefore, it is possible to provide a semiconductor integrated circuit which has an effect on the reduction of the chip size. In addition, the operation speed can be improved in comparison with the conventional circuit structure.